The PCI Special Interest Group (PCI-SIG), the group responsible for maintaining one of the most important hardware connection standards, announced the completion of first draft specification for PCI Express 7.0 (PCIe 7.0). This means that all the necessary technologies for its development are defined.
With the draft, the organization reinforces the 7th generation PCI Express performance goals. The standard is expected to offer transfer rates of up to 128 GT/s and bidirectional bandwidth of up to 512 GB/s on a 16-lane interface, ie, four times greater than the current PCI Express 5.0 standard and twice that of PCI Express 6.0, which is expected to debut in 2024.
The new specification will have 4-level pulse amplitude modulation (PAM4). This technology will be able to deliver more energy efficiency and high data transfer reliability. PCIe 7.0 must also maintain backwards compatibility with previous standards to ensure long life for graphics cards and other components.
The development of the standard is expected to be completed in mid-2025, but considering previous specification cycles, PCIe 7.0 compatible products are expected to start appearing on the market only in 2027.
PCI Express 6.0, which will succeed the current generation, had the definition of its specifications completed in January last year. The expectation is that the standard will begin to be adopted by the hardware industry in mid-2024 — possibly in segments that require maximum performance, such as supercomputing and cloud service platforms.
According to the consortium, PCIe 6.0 will offer bandwidth of up to 256 GB/s on 16-lane interfaces and a maximum transfer speed of 64 GT/s. This will be the first PCI Express specification with 4-level pulse amplitude modulation (PAM4).
