The size in nanometers is pure marketing: what does it really mean that a transistor is manufactured in 3, 5 or 7 nanometers
The nanometer thing is simply a way to differentiate some processes from others. When TSMC talks that it will start manufacturing transistors at 3 nanometers, actually this number by itself doesn’t mean anything. This size is not related to any actual physical characteristics, not the length of the logic gates or any other distance from the transistors.
When companies talk about manufacturing at 3, 5 or 7 nanometers, it does not mean that some are better than others. So much so, that the nomenclature is based solely on strategic criteria and not on a specific characteristic. And if not tell Intel, who decided to rename their nodes from 10 nanometers to 7 nanometers, those from 7 to 4 and those from 5 to 3 nanometers.
Not all nanometers are created equal
The excuse for making these name changes is found in the transistor density. Intel considered that its 10-nanometer process competed in density with TSMC’s 7-nm process and therefore chose to match the nomenclature. There was the particularity that the process of 7 nanometers from Intel (250M/mm2) surpassed in density the 5 nanometers from TSMC (171M/mm2) and hence the “sudden advance” to become 4 nanometers.
Originally nanometers used to measure the length of logic gates, but with the improvement of the different processes, nodes of different sizes began to be used. Currently, with the FinFET, VTFET or GAAFET processes, the numbers used do not correspond to any specific characteristic.
The different manufacturing processes are complex and different enough to establish a specific number for all of them.
This fact may confuse some users, but it is a widely known fact in the industry. “Today, these numbers are just numbers. They are like models of a car: it is like a BMW 5 series or a Mazda 6. It doesn’t matter what the number is, it’s just the nomenclature of the next technology, the name. Don’t confuse the name of the node with what the technology actually offers,” said Philip Wong, VP of Research at TSMC.
Let’s set the advance to 3 nanometers. It is a marketing term, yes, but justified because we are facing a new process. One advanced enough that the industry considers it a significant advance and is worthy of the name. For example, with TSMC’s 3nm FinFET, a 25-30% power reduction, 15% performance increase and up to 33% higher transistor density are promised, compared to 5nm.
But these numbers are within TSMC. In the case of Samsung it is different. And for example they promise 45% less power, 23% performance and 16% less area, compared to Samsung’s 5nm.
With downsizing it’s common to think about where the limit is. 1 nanometer is little more than the width of just five silicon atoms. But as Samuel K Moore of IEEE Spectrum points out, you have to think that “many of the parts of 7 nanometer transistors are actually considerably larger than 7 nanometers. And that disconnect between nomenclature and physical reality has been the case for about two decades.”
Still, with the advancement of photolithographic technology, the industry is already looking for new ways to describe its advanced processes. What will happen when the 1 nanometer node is improved? For a few years now, there has been talk of angstroms.
Pat Gelsinger, CEO of Intel, argued that start talking about angstroms. This way they will have more margin to define the new processes. In 2026 they hope to work with 1.4 nanometers (or 14 angstroms) and by 2030 0.7 nanometers (or 7 angstroms). These figures do not mean that the processes are going to work with exactly those distances, but they do show that the nomenclature of nanometers is beginning to fall short.
