TSMC announces its 3nm and 2nm chip development schedule
TSMC has released its chip development schedule as well as its future plans.
The schedule reveals that the Taiwan-based chipmaker will introduce its 3nm chips (N3) in the second half of this year and will also present 2nm technology sometime in 2025. The new technologies will be used to make advanced CPUs, GPUs and SoCs.
The 3nm nodes will be featured in a total of five 3nm nodes, named N3E, N3P, N3S and N3X. These N3 variants offer improved process windows, higher throughput, higher transistor densities and increased voltages for ultra-high performance applications.
All of these technologies will feature TSMC’s proprietary FINFLEX architectural innovation, which offers great flexibility to chip designers and enables them to precisely optimize chip performance, power consumption and costs.
If we talk about the 2nm technologyit will offer a noticeable improvement over the N3, with a speed increase of 10-15% at the same power, or a power reduction of 25-30% at the same speed.
N2 will come with GAAFETs (Gated Field Effect Transistors) to offer a whole node improvement in performance and power efficiency. The N2 technology platform will feature a high-performance variant, in addition to the basic mobile computing version and full chip integration solutions.
It is expected that the first N3 chips go into production in the coming months and hit the market in the first quarter of 2023. The start of N2 production is planned for 2025.
