Samsung already manufactures chips in three nanometers: they promise 23% more performance and almost twice the efficiency

Interesting movement that Samsung has just communicated. The South Korean company has announced that it has already begun initial production of its three nanometer node. He has done it by applying a processor architecture known as GAA (Gate-All-Around) and a proprietary technology called MBCFET.

According to the firm, this first-generation three-nanometer process can reduce energy consumption by “up to 45%”, improve performance “by 23%” and reduce area “by 16%” compared to the five-nanometer process. The second generation will go further, they say, consuming 50% less, improving performance by 30% and reducing the area by 35%.

Samsung makes the leap to three nanometers

To achieve this milestone, Samsung has chosen to Multi-Bridge-Channel FET (MBCFET), a Samsung GAA (Gate-All-Around) technology that has been implemented “for the first time in history” and which, according to Samsung, “defies the performance limitations of FinFET”.

This technology uses nanoplates with wider channels instead of nanowires with narrower channels. This, they explain from Samsung, allows greater performance and efficiency. Thanks to this three-nanometer GAA technology, Samsung will be able to modify the width of the channels of the plate to adjust the energy consumption and performance according to the needs of the customers.

Going to the most technical, Samsung has not only made the transistors smaller, but their structure has changed. In a transistor, current flows across the junction surface between the gate and the silicon. This is what is known as a channel.

What Samsung has done is increase the width of the channel and the number of sides. As we see in the figure above, GAA technology uses nanowires stacked on top of each other. MBCFET (Samsung’s proprietary technology) is similar, but instead of threads it uses wider nanoplates. That allows a larger amount of current to flow in a transistor with similar horizontal area.

According to Samsung, MBCFET has a lower operating voltage (the voltage required for the operation of a transistor) and allows customization to a certain extent of the design, being able to increase or decrease the width of the channel. An interesting proposal, without a doubt, that we will see implemented later.

And it is that from Samsung they claim to have initiated the application of this nanoplate transistor in “semiconductors for high performance and low consumption applications”. However, it hasplanned to extend it to mobile processors“, so it would not be strange that, sooner rather than later, we see an Exynos using this technology.

This implementation is not strictly new, as it is the one that TSMC intends to use for its future two-nanometer chipswhich we will see in 2025. The approach is practically the same and TSMC promises 30% less consumption than with N3E (three nanometers).